Cadence NCSim is a suite of tools from Cadence Design Systems related to the design and verification of ASICs, SoCs, and FPGAs. NCSim is commonly referred to by the name of its core simulation engine, which supports SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards. NCSim also offers a set of domain-specific apps, such as mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.
In this article, we will introduce some of the main features and benefits of Cadence NCSim and show how to use it for your design and verification projects.
Features and Benefits of Cadence NCSim
Cadence NCSim provides the following features and benefits for design and verification engineers:
Industry-leading simulation performance: NCSim leverages automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases.
Broad language support: NCSim supports SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards, allowing you to use your preferred language and methodology for your design and verification tasks.
Accelerate with apps: NCSim offers a portfolio of apps that work natively with the simulator and enable you to mix and match different technologies needed throughout the design and verification cycles. Some of the apps are:
Xcelium Machine Learning (ML) App: This app utilizes proprietary ML technology to reduce regression times by learning from previous regression runs and guiding the NCSim randomization kernel to either achieve the same coverage with significantly less simulation cycles or catch more bugs around specific coverage points of interest.
Xcelium Mixed-Signal (DMS) App: This app enables you to verify your mixed-signal designs using a single-kernel simulator that supports Verilog-AMS, VHDL-AMS, SPICE netlists, WREAL models, SystemVerilog real number modeling (RNM), and UVM-MS methodology.
Xcelium Multi-Core (MC) App: This app allows you to run your test cases on multiple cores or machines in parallel, reducing simulation time and improving productivity.
Xcelium Safety (SAF) App: This app helps you achieve functional safety compliance for your automotive designs by providing fault injection capabilities, fault coverage analysis, fault campaign management, and fault simulation acceleration.
Xcelium PowerPlayback (PPB) App: This app enables you to perform low-power verification using IEEE UPF standard by replaying power intent changes on top of a pre-simulated waveform database without re-running the simulation.
Xcelium X-Pessimism Removal (XPR) App: This app helps you eliminate false X-propagation issues in your RTL simulations by applying pessimism removal techniques based on structural analysis or gate-level simulations.
How to Use Cadence NCSim
To use Cadence NCSim for your design and verification projects, you need to follow these steps:
Install Cadence NCSim: You need to install Cadence NCSim on your Linux machine or use a remote server that has it installed. You also need to set up your environment variables and license file according to the installation guide.
Create a project directory: You need to create a project directory where you will store your design files, testbench files, scripts, logs, etc. You can use any directory structure that suits your needs.
Compile your design files: You need to compile your design files using one of the following commands depending on the language you are using:
ncvlog: Compiler for Verilog 95, Verilog 2001, SystemVerilog and 061ffe29dd